The present invention relates to semiconductor integrated circuit devices, and more particularly relates to techniques effective in the interface circuit for coupling other semiconductor integrated circuit device.
When a semiconductor integrated circuit device, such as an SDRAM (Synchronous Dynamic Random Access Memory), is coupled to a semiconductor integrated circuit device, such as a microcomputer, an interface circuit is required inside the respective devices. This interface circuit is designed based on a specification complying with the international standard defined for each type of SDRAM.
In the SDRAM, the DDR (Double Data Rate) standard, the DDR2 standard, the DDR3 standard, the LPDDR (Low Power Double Data Rate) standard, the LPDDR2 standard, and the like have been established.
The DDR standard includes a DDR function to read and write data at both rising and falling of the clock signal, so that data is transferred at a speed of twice the internal clock frequency of an SDRAM.
In the DDR2 standard, because the clock frequency in outputting data to the outside is twice the internal clock frequency of an SDRAM, the data can be transferred four times the internal clock frequency. In the DDR3 standard, because the clock frequency in outputting data to the outside is four times the internal clock frequency of an SDRAM, the data can be transferred eight times the internal clock frequency.
Recently, while the data transfer rate of the SDRAM has been increased, reliable data transfer is also required. In an SRAM having the DDR function, because data is taken in at both the rising edge (the rising of a waveform) and the falling edge (the falling of a waveform) of a clock signal, not only timing margins between the rising edge of a clock signal and the rising edge and falling edge of data but timing margins between the falling edge of the clock signal and the rising edge and falling edge of the data need to be considered.
Furthermore, in the case of the LPDDR2 standard, the frequency of an external clock signal is up to 533 MHz (data transfer rate is 1066 Mbps), while in the case of the DDR3 SDRAM standard, the frequency of an external clock signal is specified up to 800 MHz (data transfer rate is 1600 Mbps). As the data transfer rate increases, the data transfer period decreases and therefore it is increasingly difficult to secure the timing margins.